Responsibilities:
? Work with algorithm team and design engineers to fully understand the assigned functional blocks and develop test plan based on the architecture of ASIC.
? Implement test benches and test cases with UVM methodology.
? Responsible for functional verification on block and full chip level, work with design engineers to achieve design objectives.
? Conduct and maintain verification methodologies such as regression, code coverage and functional coverage analysis.
? Participate in RTL and post-layout gate level simulation with SDF back-annotation.
? Participate in pre-silicon validation using FPGA platform, and post-silicon bring up on EVB.
Requirements:
? MSEE and related with 1-5 years relevant verification experience.
? Familiar with System Verilog and advance UVM/VMM/OVM methodologies.
? Knowledge of OOPs concepts and C++.
? Verification experience with mixed signal design and C/SystemC/C++ co-simulation environment is a plus.
? Domain knowledge in networking ASICs, such as Ethernet PCS/PMA layer or higher layer in IP stack is definitely a plus.
? Experienced in one or more scripting languages, such as Perl, TCL, Python and Makefile.
? Good English communication and documentation skill.
職位描述：
1、與算法團隊和設(shè)計工程師合作，根據(jù)芯片架構(gòu)和設(shè)計方案制定驗證計劃；
2、完成基于UVM方法學的驗證平臺開發(fā)， 以及testcase編寫；
3、執(zhí)行模塊級和芯片級驗證、回歸測試，以及代碼覆蓋率和功能覆蓋率分析；
4、參與后仿驗證及芯片測試。
崗位要求：
1、電子、通信、集成電路等相關(guān)專業(yè)， 碩士學歷，具有3-5年及以上相關(guān)驗證經(jīng)驗；
2、熟悉Verilog、System Verilog語言，UVM/VMM/OVM驗證方法學；
3、具有混合信號設(shè)計和C/System C／C++協(xié)同仿真驗證經(jīng)驗優(yōu)先考慮；
4、熟悉以太網(wǎng)PCS/PMA層或IP協(xié)議棧優(yōu)先考慮；
5、熟悉一種或多種腳本語言，如Perl、TCL、Python或Makefile；
6、良好的中英文書面和口頭表達能力。
福利待遇:
1、固定工資、年底獎金、額外績效獎金、期權(quán)激勵、晉升培訓、每年固定調(diào)薪；
2、五險一金，補充醫(yī)療保險、享有國家規(guī)定的法定節(jié)假日及帶薪年假（年假、婚假、產(chǎn)假、病假）等待遇；
3、周末雙休、彈性工作時間；
4、定期團建、下午茶歇、過節(jié)福利、團隊聚餐、生日蛋糕、定期體檢；
5、公司提供免費單身公寓，環(huán)境好；
6、辦公環(huán)境舒適，地鐵10號線直達，附近多個公交站點，交通十分便利。
注：辦公地址：浦口。